[New post] TPU and hardware vs. software innovation (round 3)

Ray posted: "At Google IO conference this week, they revealed (see Google supercharges machine learning tasks ...) that they had been designing and operating their own processor chips in order to optimize machine learning. They called the new chip, a Tensor Processin" New post on RayOnStorage Blog TPU and hardware vs. software innovation (round 3) by Ray At Google IO conference this week, they revealed (see Google supercharges machine learning tasks ...) that they had been designing and operating their own processor chips in order to optimize machine learning. They called the new chip, a Tensor Processing Unit (TPU). According to Google, the TPU provides an order of magnitude more power efficient machine learning over what's […] Read more of this post Ray | May 19, 2016 at 12:16 pm | Tags: Commodity hardware, Custom ASIC, custom hardware, FPGA, Google, Hardware innovation, hw vs. sw differentiation, hyper-scale hive, machine intelligence, neuromorphic computing, TensorFlow, TPU | Categories: Artificial Intelligence, Cloud services, Cognitive computing, Energy efficiency, Neural network, Processing performance, Strategic Inflection Points, System effectiveness, Uncategorized, Visionary leadershp | URL: http://wp.me/pNK0N-22n Comment    See all comments Unsubscribe to no longer receive posts from RayOnStorage Blog. Change your email settings at Manage Subscriptions. Trouble clicking? Copy and paste this URL into your browser: http://silvertonconsulting.com/blog/2016/05/19/tpu-and-hardware-vs-software-innovation-round-3/